Various communication protocols using distributed clock synchronization allow multiple master devices and slave devices to communicate over a bus in a communication network without clock signal. An internal clock base for the devices is extracted from the incoming data. As a result, internal clocks in the devices must be within a certain tolerance in order to correctly communicate over the bus. Such tolerance can be easily met by crystal oscillators. However, crystal oscillators may not be desirable to implement in all devices. For example, a network may include transceivers and small slave devices that need to be able to decode messages sent on the bus and then perform actions like waking up other devices. Such devices may be required to be low cost and to have low power consumption. Therefore, on-chip oscillators provide a solution to meet these requirements, however on-chip oscillators may not be able to meet the frequency tolerance requirements of the network, especially over a wide temperature range as may required in certain applications, as well as over the lifetime of the device.
In view of the foregoing, it desirable to develop an apparatus and method so that low cost and low power oscillators may be used in network devices, yet still meet the timing requirements in the communication network using distributed clock synchronization. Devices incorporating such low-cost and low-power oscillators could then be more widely deployed in networks.